Generally, a coincidence element (hereinafter referred to as "C element") is a logical circuit which is responsive to two inputs X and Y for outputting a C or C signal in accordance with the Logic Value Table shown below. That is, the coincidence output C becomes the same level as that of the input signals when the two input signals X and Y coincide with each other, and it keeps the previous state when the two inputs X and Y are different from each other.
Such a C element is, for example, used for the transmission of transfer control pulses of an asynchronous self running shift register. Herein, an asynchronous self running shift register is one operating in such a manner that the push-in and pop-out of the data are conducted independently and simultaneously. The pushed-in data is automatically shifted towards the output without the use of shift clocks on a condition that the next stage shift register is not occupied. Such an asynchronous self running shift register functions so as to buffer data, and it can be used to connect two asynchronous systems.
______________________________________ Logic Value Table INPUT OUTPUT X Y C .sup.--C ______________________________________ 0 0 0 1 0 1 HOLD HOLD 1 0 HOLD HOLD 1 1 1 0 ______________________________________
The construction and the operation of a data transmission path comprising an asynchronous self running shift register will be described with reference to FIG. 1.
Each stage of the asynchronous self running shift register is constructed by a parallel data buffer and a transfer control circuit for controlling the opening or closing of the parallel data buffer in accordance with a control signal, and a C element is used as the transfer control circuit.
This C element opens the gate of the parallel data buffer that is provided corresponding to this C element when its C output (control signal) is 1, and the parallel data buffer receives the data transmitted from the prior stage, and holds the effective data. The C element does not open the gate of the parallel data buffer that is provided corresponding to the C element when its C output is 0, and the parallel data buffer does not receive the data from the prior stage, and does not hold the effective data. In other words, only the parallel data buffer corresponding to the C element whose C output is 1 holds the effective data, and the parallel data buffer corresponding to the C element whose C output is 0 does not hold the effective data. Herein, the C output of the C element of a particular stage is connected to the X input of the C element of the next stage, and the C output of the C element is connected to the Y input of the C element of the prior stage.
The device of FIG. 1 will be operated as follows.
Supposing that the C outputs of all the C elements 301 to 305 are 0, and the C outputs thereof are 1 at the initial state. When 1 is input to the X input of the C element 301 from the input at the left end of FIG. 1 and at the same time a data is given to the input terminal of the parallel data buffer 311, and the C output of the first C element 301 changes to 1 because both of two inputs thereof become 1, the data given to the input terminal of the parallel data buffer 311 is received thereby. Similarly as above, the C element at the second stage and that at the stage subsequent thereto receive the C output 1 of its prior stage C element, and change the C and C output of itself to 1 and to 0, respectively, thereby opening the gate of the parallel data buffer of that stage to make the parallel data buffer hold the data transmitted from the prior stage. Next, when 0 is input to the X input of the C element 301 from the input terminal at the left end of FIG. 1, the C and C output of the C element becomes 0 and 1, respectively, in turn from the left end because the Y inputs of the C elements 301 to 305 are all 0.
When a pulse signal is given to the X input of the C element 301 at the left end of the shift register and a data is input to the parallel data buffer 311 at the left end while the pulse signal is 1 as described above, the data is pushed in into the shift register. The signal 1 input to the X input of the C element 301 is transmitted to the right from the left together with the input data as shown in FIG. 1. Besides, when the level of the signal input to the X input of the C element 301 is changed to 0 from 1, the signal level 0 is transmitted from the left to the right. However, when the initial value of the C output of the right end C element 305 is 0, the C output of the C element 305 is kept 0 regardless of the fact that the X input thereof is changed to 1 caused by that the C output of the prior stage is changed to 1. Then, the Y input of the C element 304 at its prior stage is 1, and therefore, the output of the C element 304 is kept 1 with no change regardless of the fact that the C output of the prior stage C element 303 is transmitted to that stage. Accordingly, the signal level 0 of the C output of the C element does not outrun 1, or make the 1 forfeit.
As described above, when a push-in operation from the left end shift register is conducted by keeping the Y input of the right end C element 305 0, the outputs of the C elements become 0, 1, 0, 1, . . . , respectively, from the right end C element 305 towards leftwards. Furthermore, when the Y input of the right end C element 305 is changed to 1, the C output of the right end C element 305 is changed to 1 because the two inputs of the right end C element 305 become 1, and the C outputs of the C elements becomes in turn 1, 0, 1, 0, 1, . . . , respectively, from the right end, and the first word data which is pushed into the shift register from the left end is output at the output terminal of the parallel data buffer 315. In this way, the data pushed into the shift register from the left end parallel data buffer 311 is popped out by applying pulse signals to the Y input of the right end C element 305.
In the above description, the push-in operation and the pop-out operation are described distinctly from each other for simplification, but both operations can be conducted at the same time. This means that this asynchronous self running shift register has the same data buffering function as that of an asynchronous FIFO (first-in first-out) memory, and the push-in and the pop-out operation can be conducted by applying pulse signals to the X input of the right end C element 301 and to the Y input of the right end C element 305, respectively.
Conventionally, a C element constituted by logic gates, which is described in an article "An Elastic Memory Device Comprising a Non-synchronous Delay Line", recited in Journal of Electronics and Communication Society, November 1967, pp 84 to 91, is generally used as a transfer control circuit in a data transmission path.
FIG. 2 shows a construction of one stage of the C element shown in FIG. 5 of the above-described article. In FIG. 2, the reference numerals 501 to 503 designate two input AND gates, the reference numeral 504 designates a three input OR gate, and the reference numeral 505 designates an inverter.
The device will be operated as follows.
When the two inputs X and Y are both 1, the output of the AND gate 502 becomes 1, the output of the OR gate 504 becomes 1, and thus 1 and 0 are output at the C and C output, respectively. When the both of the two inputs X and Y are 0, the outputs of the AND gates 501 to 503 become all 0, the output of the OR gate 504 becomes 0, and thus 0 and 1 are output at the C and C output, respectively. Furthermore, when 1 and 0 are input at the X and Y input, respectively, with the C output before the signals X and Y are input being A (1 or 0), the outputs of the AND gate 502 and 503 become 0, the output of the AND gate 501 becomes A (1 or 0), the output of the OR gate 504 becomes A, and thus the C and C output become A and A, respectively, holding the previous states. The operation of the device when the inputs X and Y are 0 and 1, respectively, is similar as that when the inputs X and Y are 1 and 0, respectively.
The conventional C element with such a construction, has a disadvantage in that it should have a large number of gate stages, leading to a long transmission delay when it is constituted by CMOS logic gates for the purpose of reducing the power consumption. Furthermore, when this C element is used as a transfer control circuit in a data transmission path, the circuit size of the data transmission path becomes large, and the speed of data transmission becomes low.